/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * NAU88L11 ALSA SoC audio driver
 *
 * Copyright 2022 Nuvoton Technology Corp.
 * Author: David Lin <ctlin0@nuvoton.com>
 */

#ifndef __NAU8811_H__
#define __NAU8811_H__

#define NAU8811_R00_RESET			0x00
#define NAU8811_R01_ENA_CTRL			0x01
#define NAU8811_R03_CLK_DIVIDER			0x03
#define NAU8811_R08_PDB_CTL			0x08
#define NAU8811_R0F_INTERRUPT_MASK		0x0f
#define NAU8811_R10_IRQ_STATUS			0x10
#define NAU8811_R11_INT_CLR_KEY_STATUS		0x11
#define NAU8811_R12_INTERRUPT_DIS_CTRL		0x12
#define NAU8811_R13_DMIC_CTRL			0x13
#define NAU8811_R1B_TDM_CTRL			0x1b
#define NAU8811_R1C_I2S_PCM_CTRL1		0x1c
#define NAU8811_R1D_I2S_PCM_CTRL2		0x1d
#define NAU8811_R1E_LEFT_TIME_SLOT		0x1e
#define NAU8811_R21_BIQ0_COF1			0x21
#define NAU8811_R22_BIQ0_COF2			0x22
#define NAU8811_R23_BIQ0_COF3			0x23
#define NAU8811_R24_BIQ0_COF4			0x24
#define NAU8811_R25_BIQ0_COF5			0x25
#define NAU8811_R26_BIQ0_COF6			0x26
#define NAU8811_R27_BIQ0_COF7			0x27
#define NAU8811_R28_BIQ0_COF8			0x28
#define NAU8811_R29_BIQ0_COF9			0x29
#define NAU8811_R2A_BIQ0_COF10			0x2a
#define NAU8811_R2B_ADC_RATE			0x2b
#define NAU8811_R2C_DAC_CTRL1			0x2c
#define NAU8811_R2D_DAC_CTRL2			0x2d
#define NAU8811_R30_ADC_DGAIN_CTRL		0x30
#define NAU8811_R31_MUTE_CTRL			0x31
#define NAU8811_R34_DAC_DGAIN_CTRL		0x34
#define NAU8811_R35_ADC_DGAIN_CTRL1		0x35
#define NAU8811_R36_ADC_DRC_KNEE_IP12		0x36
#define NAU8811_R37_ADC_DRC_KNEE_IP34		0x37
#define NAU8811_R38_ADC_DRC_SLOPES		0x38
#define NAU8811_R39_ADC_DRC_ATKDCY		0x39
#define NAU8811_R3A_DAC_DRC_KNEE_IP12		0x3a
#define NAU8811_R3B_DAC_DRC_KNEE_IP34		0x3b
#define NAU8811_R3C_DAC_DRC_SLOPES		0x3c
#define NAU8811_R3D_DAC_DRC_ATKDCY		0x3d
#define NAU8811_R41_BIQ1_COF1			0x41
#define NAU8811_R42_BIQ1_COF2			0x42
#define NAU8811_R43_BIQ1_COF3			0x43
#define NAU8811_R44_BIQ1_COF4			0x44
#define NAU8811_R45_BIQ1_COF5			0x45
#define NAU8811_R46_BIQ1_COF6			0x46
#define NAU8811_R47_BIQ1_COF7			0x47
#define NAU8811_R48_BIQ1_COF8			0x48
#define NAU8811_R49_BIQ1_COF9			0x49
#define NAU8811_R4A_BIQ1_COF10			0x4a
#define NAU8811_R4C_IMM_MODE_CTRL		0x4c
#define NAU8811_R51_VCM_BUF			0x51
#define NAU8811_R52_SPK_DRV			0x52
#define NAU8811_R53_SPG_AMP_OFFSETDEC		0x53
#define NAU8811_R55_MISC_CTRL			0x55
#define NAU8811_R58_I2C_DEVICE_ID		0x58
#define NAU8811_R59_SARDOUT_RAM_STATUS		0x59
#define NAU8811_R66_BIAS_ADJ			0x66
#define NAU8811_R69_SPARE_ANALOG		0x69
#define NAU8811_R6B_MUTE_CTL			0x6b
#define NAU8811_R71_ANALOG_ADC_1		0x71
#define NAU8811_R72_ANALOG_ADC_2		0x72
#define NAU8811_R73_DAC_CTRL			0x73
#define NAU8811_R74_MIC_BIAS			0x74
#define NAU8811_R76_BOOST			0x76
#define NAU8811_R77_FEPGA			0x77
#define NAU8811_R7E_PGA_GAIN			0x7e
#define NAU8811_R7F_POWER_UP_CONTROL		0x7f
#define NAU8811_R82_GENERAL_STATUS		0x82
#define NAU8811_REG_MAX				NAU8811_R82_GENERAL_STATUS
/* 16-bit control register address, and 16-bits control register data */
#define NAU8811_REG_ADDR_LEN			16
#define NAU8811_REG_DATA_LEN			16

/* ENA_CTRL (0x01) */
#define NAU8811_CMLCK_ENB_SFT			15
#define NAU8811_CMLCK_ENB_DIS			(0x1 << NAU8811_CMLCK_ENB_SFT)
#define NAU8811_CLK_DAC_INV_SFT			14
#define NAU8811_CLK_DAC_INV			(0x1 << NAU8811_CLK_DAC_SFT)
#define NAU8811_DACEN_SFT			13
#define NAU8811_DACEN				(0x1 << NAU8811_DACEN_SFT)
#define NAU8811_ADCEN_SFT			12
#define NAU8811_ADCEN				(0x1 << NAU8811_ADCEN_SFT)
#define NAU8811_DCLK_ADC_EN_SFT			11
#define NAU8811_DCLK_ADC_EN			(0x1 << NAU8811_DCLK_ADC_EN_SFT)
#define NAU8811_DCLK_DAC_EN_SFT			10
#define NAU8811_DCLK_DAC_EN			(0x1 << NAU8811_DCLK_DAC_EN_SFT)
#define NAU8811_CLK_BIST_EN_SFT			8
#define NAU8811_CLK_BIST_EN			(0x1 << NAU8811_CLK_BIST_EN_SFT)
#define NAU8811_CLK_I2S_EN_SFT			7
#define NAU8811_CLK_I2S_EN			(0x1 << NAU8811_CLK_I2S_EN_SFT)
#define NAU8811_CLK_DRC_EN_SFT			6
#define NAU8811_CLK_DRC_EN			(0x1 << NAU8811_CLK_DRC_EN_SFT)
#define NAU8811_MCLK_RNG_SEL_SFT		3
#define NAU8811_MCLK_RNG_SEL_MASK		(0x7 << NAU8811_MCLK_RNG_SEL_SFT)
#define NAU8811_MCLK_RNG_SEL_0			(0x0 << NAU8811_MCLK_RNG_SEL_SFT)
#define NAU8811_MCLK_RNG_SEL_4			(0x4 << NAU8811_MCLK_RNG_SEL_SFT)
#define NAU8811_MCLK_RNG_SEL_7			(0x7 << NAU8811_MCLK_RNG_SEL_SFT)
#define NAU8811_SYSCLK_SEL_MASK			0x1
#define NAU8811_SYSCLK_SEL_MCLK			0x0
#define NAU8811_SYSCLK_SEL_2MCLK		0x1

/* CLK_DIVIDER (0x03) */
#define NAU8811_CLK_CODEC_SRC_SFT		13
#define NAU8811_CLK_CODEC_SRC_MASK		(0x1 << NAU8811_CLK_CODEC_SRC_SFT)
#define NAU8811_CLK_CODEC_SRC_EXT_MCLK	(0x1 << NAU8811_CLK_CODEC_SRC_SFT)
#define NAU8811_CLK_CODEC_SRC_INT_MCLK	(0x0 << NAU8811_CLK_CODEC_SRC_SFT)
#define NAU8811_DLK_DAC_PL_SFT			11
#define NAU8811_DLK_DAC_PL			(0x1 << NAU8811_DLK_DAC_PL_SFT)
#define NAU8811_DLK_ADC_PL_SFT			10
#define NAU8811_DLK_ADC_PL			(0x1 << NAU8811_DLK_ADC_PL_SFT)
#define NAU8811_CLK_ADC_SRC_SFT			6
#define NAU8811_CLK_ADC_SRC_MASK		(0x3 << NAU8811_CLK_ADC_SRC_SFT)
#define NAU8811_CLK_DAC_SRC_SFT			4
#define NAU8811_CLK_DAC_SRC_MASK		(0x3 << NAU8811_CLK_DAC_SRC_SFT)
#define NAU8811_CLK_MCLK_SRC_MASK		0x7

/* R08 (0x08) */
#define NAU8811_PDB_DAC_SFT			15
#define NAU8811_PDB_DAC_DIS			(0x0 << NAU8811_PDB_DAC_SFT)
#define NAU8811_PDB_DAC_EN			(0x1 << NAU8811_PDB_DAC_SFT)

/* INTERRUPT_MASK (0x0f) */
#define NAU8811_APR_EMRG_SHTDWN_INTP		(0x1 << 9)
#define NAU8811_KEY_RELEASE_INTP		(0x1 << 7)
#define NAU8811_KEY_PRESS_INTP			(0x1 << 6)
#define NAU8811_MCLKDET_INTP			(0x1 << 5)
#define NAU8811_MIC_DET_INTP			(0x1 << 4)

/* IRQ_STATUS (0x10) */
#define NAU8811_APR_EMRG_SHTDWN_IRQ		(0x1 << 9)
#define NAU8811_KEY_RELEASE_IRQ			(0x1 << 7)
#define NAU8811_KEY_PRESS_IRQ			(0x1 << 6)
#define NAU8811_MCLK_DET_IRQ			(0x1 << 5)
#define NAU8811_MIC_DET_IRQ			(0x1 << 4)

/* INTERRUPT_DIS_CTRL (0x12) */
#define NAU8811_APR_EMRG_SHTDWN_INT_DIS		(0x1 << 9)
#define NAU8811_KEY_RELEASE_INT_DIS		(0x1 << 7)
#define NAU8811_MCLKDET_INT_DIS			(0x1 << 6)
#define NAU8811_MIC_DET_INT_DIS			(0x1 << 5)

/* DMIC_CTRL (0x13) */
#define NAU8811_DMIC_DS_SFT			11
#define NAU8811_DMIC_DS_MASK			(0x1 << NAU8811_DMIC_DS_SFT)
#define NAU8811_DMIC_DS_HIGH			(0x1 << NAU8811_DMIC_DS_SFT)
#define NAU8811_DMIC_DS_LOW			(0x0 << NAU8811_DMIC_DS_SFT)
#define NAU8811_DMIC_SLEW_SFT			8
#define NAU8811_DMIC_SLEW_MASK			(0x7 << NAU8811_DMIC_SLEW_SFT)
#define NAU8811_CLK_DMIC_SRC_SFT		1
#define NAU8811_CLK_DMIC_SRC_MASK		(0x3 << NAU8811_CLK_DMIC_SRC_SFT)
#define NAU8811_CLK_ADC_DIV_1			(0x0 << NAU8811_CLK_DMIC_SRC_SFT)
#define NAU8811_CLK_ADC_DIV_2			(0x1 << NAU8811_CLK_DMIC_SRC_SFT)
#define NAU8811_CLK_ADC_DIV_4			(0x2 << NAU8811_CLK_DMIC_SRC_SFT)
#define NAU8811_CLK_ADC_DIV_8			(0x3 << NAU8811_CLK_DMIC_SRC_SFT)
#define NAU8811_DMICEN_SFT			0
#define NAU8811_DMICEN_EN			1

/* TDM_CTRL (0x1b) */
#define NAU8811_TDM_EN_SFT			15
#define NAU8811_TDM_EN				(0x1 << NAU8811_TDM_EN_SFT)
#define NAU8811_PCM_OFFSET_MODE_CTRL_SFT	14
#define NAU8811_PCM_OFFSET_MODE_CTRL_EN		(0x1 << NAU8811_PCM_OFFSET_MODE_CTRL_SFT)
#define NAU8811_ADCPHS0_SFT			13
#define NAU8811_ADCPHS0_INV			(0x1 << NAU8811_ADCPHS0_SFT)
#define NAU8811_DACPHS0_SFT			11
#define NAU8811_DACPHS0_INV			(0x1 << NAU8811_DACPHS0_SFT)
#define NAU8811_DAC_SEL_SFT			7
#define NAU8811_DAC_SEL_MASK			(0x7 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT0			(0x0 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT1			(0x1 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT2			(0x2 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT3			(0x3 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT4			(0x4 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT5			(0x5 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT6			(0x6 << NAU8811_DAC_SEL_SFT)
#define NAU8811_DAC_SEL_SLOT7			(0x7 << NAU8811_DAC_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SFT			2
#define NAU8811_ADC_TX_SEL_MASK			(0x7 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT0		(0x0 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT1		(0x1 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT2		(0x2 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT3		(0x3 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT4		(0x4 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT5		(0x5 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT6		(0x6 << NAU8811_ADC_TX_SEL_SFT)
#define NAU8811_ADC_TX_SEL_SLOT7		(0x7 << NAU8811_ADC_TX_SEL_SFT)

/* I2S_PCM_CTRL1 (0x1c) */
#define NAU8811_DACCM0_SFT			14
#define NAU8811_DACCM0_MASK			(0x3 << NAU8811_DACCM0_SFT)
#define NAU8811_ADCCM0_SFT			12
#define NAU8811_ADCCM0_MASK			(0x3 << NAU8811_ADCCM0_SFT)
#define NAU8811_ADDAP0_SFT			11
#define NAU8811_ADDAP0_EN			(0x1 << NAU8811_ADDAP0_SFT)
#define NAU8811_CMB8_0_SFT			10
#define NAU8811_CMB8_0_EN			(0x1 << NAU8811_CMB8_0_SFT)
#define NAU8811_UA_OFFSET_SFT			9
#define NAU8811_UA_OFFSET_2CMP			(0x1 << NAU8811_UA_OFFSET_SFT)
#define NAU8811_BCP0_SFT			7
#define NAU8811_BCP0_MASK			(0x1 << NAU8811_BCP0_SFT)
#define NAU8811_BCP0_INV			(0x1 << NAU8811_BCP0_SFT)
#define NAU8811_LRP0_SFT			6
#define NAU8811_LRP0_MASK			(0x1 << NAU8811_LRP0_SFT)
#define NAU8811_LRP0_PCMB_EN			(0x1 << NAU8811_LRP0_SFT)
#define NAU8811_WLEN0_SFT			2
#define NAU8811_WLEN0_MASK			(0x3 << NAU8811_WLEN0_SFT)
#define NAU8811_WLEN0_16			(0x0 << NAU8811_WLEN0_SFT)
#define NAU8811_WLEN0_20			(0x1 << NAU8811_WLEN0_SFT)
#define NAU8811_WLEN0_24			(0x2 << NAU8811_WLEN0_SFT)
#define NAU8811_WLEN0_32			(0x3 << NAU8811_WLEN0_SFT)
#define NAU8811_AIFMT0_MASK			0x3
#define NAU8811_AIFMT0_LEFT			0x0
#define NAU8811_AIFMT0_RIGHT			0x1
#define NAU8811_AIFMT0_I2S			0x2
#define NAU8811_AIFMT0_PCM_AB			0x3

/* I2S_PCM_CTRL2 (0x1d) */
#define NAU8811_I2S_TRI_SFT			15
#define NAU8811_I2S_TRI				(0x1 << NAU8811_I2S_TRI_SFT)
#define NAU8811_I2S_DRV_SFT			14
#define NAU8811_I2S_DRV_EN			(0x1 << NAU8811_I2S_DRV_SFT)
#define NAU8811_LRC_DIV_SFT			12
#define NAU8811_LRC_DIV_MASK			(0x3 << NAU8811_LRC_DIV_SFT)
#define NAU8811_LRC_DIV_256			(0x0 << NAU8811_LRC_DIV_SFT)
#define NAU8811_LRC_DIV_128			(0x1 << NAU8811_LRC_DIV_SFT)
#define NAU8811_LRC_DIV_64			(0x2 << NAU8811_LRC_DIV_SFT)
#define NAU8811_LRC_DIV_32			(0x3 << NAU8811_LRC_DIV_SFT)
#define NAU8811_PCM_TS_SFT			10
#define NAU8811_PCM_TS_EN			(0x1 << NAU8811_PCM_TS_SFT)
#define NAU8811_TRI0_SFT			9
#define NAU8811_TRI0_EN				(0x1 << NAU8811_TRI0_SFT)
#define NAU8811_PCM8BIT0_SFT			8
#define NAU8811_PCM8BIT0_EN			(0x1 << NAU8811_PCM8BIT0_SFT)
#define NAU8811_ADCDAT0_PE_SFT			6
#define NAU8811_ADCDAT0_PE_EN			(0x1 << NAU8811_ADCDAT0_PE_SFT)
#define NAU8811_ADCDAT0_PS_SFT			5
#define NAU8811_ADCDAT0_PS_PULLUP		(0x1 << NAU8811_ADCDAT0_PS_SFT)
#define NAU8811_ADCDAT0_OE_SFT			4
#define NAU8811_ADCDAT0_OE_EN			(0x1 << NAU8811_ADCDAT0_OE_SFT)
#define NAU8811_MS0_SFT				3
#define NAU8811_MS_MASK				(0x1 << NAU8811_MS0_SFT)
#define NAU8811_MS_SLAVE			(0x0 << NAU8811_MS0_SFT)
#define NAU8811_MS_MASTER			(0x1 << NAU8811_MS0_SFT)
#define NAU8811_BCLKDIV_MASK			0x7
#define NAU8811_BCLKDIV_1			0x0
#define NAU8811_BCLKDIV_2			0x1
#define NAU8811_BCLKDIV_4			0x2
#define NAU8811_BCLKDIV_8			0x3
#define NAU8811_BCLKDIV_16			0x4
#define NAU8811_BCLKDIV_32			0x5

/* LEFT_TIME_SLOT (0x1e) */
#define NAU8811_FS_ERR_CMP_SEL_SFT		14
#define NAU8811_FS_ERR_CMP_SEL_MASK		(0x3 << NAU8811_FS_ERR_CMP_SEL_SFT)
#define NAU8811_DIS_FS_SHORT_DET_SFT		13
#define NAU8811_DIS_FS_SHORT_DET_DIS		(0x1 << NAU8811_DIS_FS_SHORT_DET_SFT)
#define NAU8811_TSLOT_L0_MASK			0x3ff

/* BIQ0_COF10 (0x2a) */
#define NAU8811_BIQ0_EN_SFT			3
#define NAU8811_BIQ0_ADC_EN			(0x1 << NAU8811_BIQ0_EN_SFT)

/* ADC_RATE (0x2b) */
#define NAU8811_ADC_SRC_SFT			15
#define NAU8811_ADC_SRC_LATCH_RIGHT		(0x1 << NAU8811_ADC_SRC_SFT)
#define NAU8811_SMPL_RATE_SFT			5
#define NAU8811_SMPL_RATE_MASK			(0x7 << NAU8811_SMPL_RATE_SFT)
#define NAU8811_SMPL_RATE_48K			(0x0 << NAU8811_SMPL_RATE_SFT)
#define NAU8811_SMPL_RATE_32K			(0x1 << NAU8811_SMPL_RATE_SFT)
#define NAU8811_SMPL_RATE_96K			(0x6 << NAU8811_SMPL_RATE_SFT)
#define NAU8811_SMPL_RATE_192K			(0x7 << NAU8811_SMPL_RATE_SFT)
#define NAU8811_OSR_ADC_RATE_SFT		0
#define NAU8811_OSR_ADC_RATE_MASK		0x3
#define NAU8811_OSR_ADC_RATE_DOWN_32		0x0
#define NAU8811_OSR_ADC_RATE_DOWN_64		0x1
#define NAU8811_OSR_ADC_RATE_DOWN_128		0x2
#define NAU8811_OSR_ADC_RATE_DOWN_256		0x3

/* DAC_CTRL1 (0x2c) */
#define NAU8811_CICCLP_OFF_SFT			7
#define NAU8811_CICCLP_OFF_MASK			(0x1 << NAU8811_CICCLP_OFF_SFT)
#define NAU8811_CICCLP_OFF_EN			(0x1 << NAU8811_CICCLP_OFF_SFT)
#define NAU8811_CICCLP_OFF_DIS			(0x0 << NAU8811_CICCLP_OFF_SFT)
#define NAU8811_CIC_GAIN_ADJ_SFT		4
#define NAU8811_CIC_GAIN_ADJ_MASK		(0x7 << NAU8811_CIC_GAIN_ADJ_SFT)
#define NAU8811_OSR_DAC_RATE_SFT		0
#define NAU8811_OSR_DAC_RATE_MASK		0x7
#define NAU8811_OSR_DAC_RATE_DOWN_32		0x4
#define NAU8811_OSR_DAC_RATE_DOWN_64		0x0
#define NAU8811_OSR_DAC_RATE_DOWN_128		0x2
#define NAU8811_OSR_DAC_RATE_DOWN_256		0x1

/* DAC_CTRL2 (0x2d) */
#define NAU8811_SDMOD_DITHER_SFT		8
#define NAU8811_SDMODE_DITHER_MASK		(0xf << NAU8811_SDMOD_DITHER_SFT)

/* ADC_DGAIN_CTR (0x30) */
#define NAU8811_ADC_TO_DAC_ST0_SFT		12
#define NAU8811_ADC_TO_DAC_ST0_MASK		(0xf << NAU8811_ADC_TO_DAC_ST0_SFT)

/* MUTE_CTRL (0x31) */
#define NAU8811_DAC_SLOW_UM_SFT			13
#define NAU8811_DAC_SLOW_UM_EN			(0x1 << NAU8811_DAC_SLOW_UM_SFT)
#define NAU8811_DAC_ZC_SFT			12
#define NAU8811_DAC_ZC_EN			(0x1 << NAU8811_DAC_ZC_SFT)
#define NAU8811_AMUTE_SFT			11
#define NAU8811_AMUTE_EN			(0x1 << NAU8811_AMUTE_SFT)
#define NAU8811_AMUTE_CTRL_SFT			10
#define NAU8811_AMUTE_CTRL_EN			(0x1 << NAU8811_AMUTE_CTRL_SFT)
#define NAU8811_SMUTE_SFT			9
#define NAU8811_SMUTE_EN			(0x1 << NAU8811_SMUTE_SFT)
#define NAU8811_ADC_ZC_SFT			2
#define NAU8811_ADC_ZC_EN			(0x1 << NAU8811_ADC_ZC_SFT)
#define NAU8811_ADC_SMUTE_SFT			1
#define NAU8811_ADC_SMUTE_EN			(0x1 << NAU8811_ADC_SMUTE_SFT)

/* DAC_DGAIN_CTRL (0x34) */
#define NAU8811_DGAIN_DAC_SFT			0
#define NAU8811_DGAIN_DAC_MASK			0xff

/* ADC_DGAIN_CTRL (0x35) */
#define NAU8811_DGAIN_ADC_SFT			0
#define NAU8811_DGAIN_ADC_MASK			0xff

/* BIQ1_COF10 (0x4a) */
#define NAU8811_BIQ1_EN_SFT			3
#define NAU8811_BIQ1_DAC_EN			(0x1 << NAU8811_BIQ1_EN_SFT)

/* VCM_BUF (0x51) */
#define NAU8811_VCM_GAIN_CTRL_SFT		6
#define NAU8811_VCM_GAIN_CTRL_MASK		(0xf << NAU8811_VCM_GAIN_CTRL_SFT)
#define NAU8811_PDB_VCMBUF_SFT			5
#define NAU8811_PDB_VCMBUF_MASK			(0x1 << NAU8811_PDB_VCMBUF_SFT)
#define NAU8811_PDB_VCMBUF_EN			(0x1 << NAU8811_PDB_VCMBUF_SFT)
#define NAU8811_VOUT_PRECHG_DISABLE_SFT		4
#define NAU8811_VOUT_PRECHG_DISABLE_MASK	(0x1 << NAU8811_VOUT_PRECHG_DISABLE_SFT)
#define NAU8811_VOUT_PRECHG_DISABLE_OFF		(0x0 << NAU8811_VOUT_PRECHG_DISABLE_SFT)
#define NAU8811_VOUT_PRECHG_DISABLE_ON		(0x1 << NAU8811_VOUT_PRECHG_DISABLE_SFT)
#define NAU8811_PRECHG_IB_CTRL_SHT		2
#define NAU8811_PRECHG_IB_CTRL_MASK		(0x3 << NAU8811_PRECHG_IB_CTRL_SHT)

/* SPK_DRV (0x52) */
#define NAU8811_MUTE_SPK_SFT			8
#define NAU8811_MUTE_SPK_EN			(0x1 << NAU8811_MUTE_SPK_SFT)
#define NAU8811_MDRV_IB_SEL_SFT			6
#define NAU8811_MDRV_IB_SEL_MASK		(0x3 << NAU8811_MDRV_IB_SEL_MASK)
#define NAU8811_PUP_MAIN_DRV_SFT		5
#define NAU8811_PUP_MAIN_DRV_EN			(0x1 << NAU8811_PUP_MAIN_DRV_SFT)
#define NAU8811_SPK_GAIN_CNTRL_MASK		0xf
#define NAU8811_SPK_GAIN_CNTRL_SFT		0

/* SPG_AMP_OFFSETDEC (0x53) */
#define NAU8811_CAL_SGN_SFT			4
#define NAU8811_EN_CAL_SFT			3
#define NAU8811_OFFSET_CALS_MASK		0x7

/* MISC_CTRL (0x55) */
#define NAU8811_D2A_LOOP_SFT			1
#define NAU8811_D2A_LOOP_EN			(0x1 << NAU8811_D2A_LOOP_SFT)

/* I2C_DEVICE_ID (0x58) */
#define NAU8811_I2C_DEVICE_ID_SFT		8
#define NAU8811_I2C_DEVICE_ID_MASK		(0x7f << NAU8811_I2C_DEVICE_ID_SFT)
#define NAU8811_SILICON_REVISION_ID_MASK	0x3f

/* BIAS_ADJ (0x66) */
#define NAU8811_MUTE_SFT			13
#define NAU8811_MUTE_PGA_EN			(0x1 << NAU8811_MUTE_SFT)
#define NAU8811_TESTDAC_SFT			8
#define NAU8811_TESTDAC_EN			(0x1 << NAU8811_TESTDAC_SFT)
#define NAU8811_VMIDEN_SFT			6
#define NAU8811_VMIDEN_EN			(0x1 << NAU8811_VMIDEN_SFT)
#define NAU8811_VMIDSEL_SFT			4
#define NAU8811_VMIDSEL_MASK			(0x3 << NAU8811_VMIDSEL_SFT)
#define NAU8811_BIASADJ_MASK			0x3

/* SPARE_ANALOG1 (0x69) */
#define NAU8811_PULL_SPKR_DWN_SFT		15
#define NAU8811_PULL_SPKR_DWN_EN		(0x1 << NAU8811_PULL_SPKR_DWN_SFT)
#define NAU8811_PRECHG_CURR_BOOST_SFT		14
#define NAU8811_PRECHG_CURR_BOOST_EN		(0x1 << NAU8811_PRECHG_CURR_BOOST_SFT)
#define NAU8811_PRECHG_CURR_TRUBO_SFT		13
#define NAU8811_PRECHG_CURR_TRUBO_EN		(0x1 << NAU8811_PRECHG_CURR_TRUBO_SFT)
#define NAU8811_THD_BOOST_SFT			5
#define NAU8811_THD_BOOST_EN			(0x1 << NAU8811_THD_BOOST_SFT)
#define NAU8811_TESTDACIN_SFT			2
#define NAU8811_TESTDACIN_MASK			(0x3 << NAU8811_TESTDACIN_SFT)
#define NAU8811_CAP_MASK			0x3

/* MUTE_CTRL (0x6b) */
#define NAU8811_MUTE_MICN_SFT			5
#define NAU8811_MUTE_MICN_EN			(0x1 << NAU8811_MUTE_MICN_SFT)
#define NAU8811_MUTE_MICP_SFT			3
#define NAU8811_MUTE_MICP_EN			(0x1 << NAU8811_MUTE_MICP_SFT)

/* ANALOG_ADC_2 (0x72) */
#define NAU8811_ADC_UP_SFT			13
#define NAU8811_ADC_UP_EN			(0x1 << NAU8811_ADC_UP_SFT)
#define NAU8811_BIAS_SFT			10
#define NAU8811_BIAS_MASK			(0x3 << NAU8811_BIAS_SFT)
#define NAU8811_VREFSEL_SFT			8
#define NAU8811_VREFSEL_MASK			(0x3 << NAU8811_VREFSEL_SFT)
#define NAU8811_PDNOT_SFT			6
#define NAU8811_PDNOT_EN			(0x1 << NAU8811_PDNOT_SFT)

/* DAC_CTRL (0x73) */
#define NAU8811_DAC_SFT				12
#define NAU8811_DAC_EN				(0x1 << NAU8811_DAC_SFT)
#define NAU8811_CLK_DAC_SFT			8
#define NAU8811_CLK_DAC_EN			(0x1 << NAU8811_CLK_DAC_SFT)
#define NAU8811_FC_CTR_SFT			7
#define NAU8811_FC_CTR_EN			(0x1 << NAU8811_FC_CTR_SFT)
#define NAU8811_CLK_DAC_DELAY_SFT		4
#define NAU8811_CLK_DAC_DELAY_MASK		(0x7 << NAU8811_CLK_DAC_DELAY_SFT)
#define NAU8811_DACVREFSEL_SFT			2
#define NAU8811_DACVREFSEL_MASK			(0x3 << NAU8811_DACVREFSEL_SFT)

/* MIC_BIAS (0x74) */
#define NAU8811_POWERUP_SFT			8
#define NAU8811_MB_LPMODE_SFT			3
#define NAU8811_MB_LPMODE_MASK			(0x3 << NAU8811_MB_LPMODE_SFT)
#define NAU8811_MICBIASLVL1_MASK		0x7

/* BOOST (0x76) */
#define NAU8811_CLR_APR_EMRG_SHTDWN_SFT		15
#define NAU8811_CLR_APR_EMRG_SHTDWN_RST		(0x1 << NAU8811_CLR_APR_EMRG_SHTDWN_SFT)
#define NAU8811_STG2_SEL_SFT			14
#define NAU8811_STG2_SEL_EN			(0x1 << NAU8811_STG2_SEL_SFT)
#define NAU8811_PDVMDFST_SFT			13
#define NAU8811_PDVMDFST_DIS			(0x1 << NAU8811_PDVMDFST_SFT)
#define NAU8811_BIASEN_SFT			12
#define NAU8811_BIASEN_EN			(0x1 << NAU8811_BIASEN_SFT)
#define NAU8811_DISCHRG_SFT			11
#define NAU8811_DISCHRG_EN			(0x1 << NAU8811_DISCHRG_SFT)
#define NAU8811_RST_SHRT_IRQ_SFT		7
#define NAU8811_RST_SHRT_IRQ_EN			(0x1 << NAU8811_RST_SHRT_IRQ_SFT)
#define NAU8811_DISABLE_SHRT_DET_SFT		6
#define NAU8811_DISABLE_SHRT_DET_EN		(0x1 << NAU8811_DISABLE_SHRT_DET_SFT)

/* FEPGA (0x77) */
#define NAU8811_ACDC_CTRL_SFT			14
#define NAU8811_ACDC_CTRL_MASK			(0x3 << NAU8811_ACDC_CTRL_SFT)
#define NAU8811_ACDC_CTRL_MICP			(0x1 << NAU8811_ACDC_CTRL_SFT)
#define NAU8811_ACDC_CTRL_MICN			(0x2 << NAU8811_ACDC_CTRL_SFT)
#define NAU8811_CMLCK_ADJ_SFT			12
#define NAU8811_CMLCK_ADJ_MASK			(0x3 << NAU8811_CMLCK_ADJ_SFT)
#define NAU8811_IB_LOOP_CTR_SFT			11
#define NAU8811_IB_LOOP_CTR_MASK		(0x1 << NAU8811_IB_LOOP_CTR_SFT)
#define NAU8811_IBCTR_CODE_SFT			8
#define NAU8811_IBCTR_CODE_MASK			(0x7 << NAU8811_IBCTR_CODE_SFT)
#define NAU8811_PGA_MODE_SFT			4
#define NAU811_PGA_MODE_MASK			(0xf << NAU8811_PGA_MODE_SFT)

/* PGA_GAIN (0x7e) */
#define NAU8811_PGA_GAIN_SFT			8
#define NAU8811_PGA_GAIN_MASK			(0x3f << NAU8811_PGA_GAIN_SFT)

/* POWER_UP_CONTROL (0x7f) */
#define NAU8811_PUPL_SFT			15
#define NAU8811_PUPL_MASK			(0x1 << NAU8811_PUPL_SFT)
#define NAU8811_PUPL_EN				(0x1 << NAU8811_PUPL_SFT)

#define NUVOTON_CODEC_DAI "nau8811-hifi"

struct nau8811 {
	struct device *dev;
	struct regmap *regmap;
	int micbias_voltage;
	int vref_impedance;
	unsigned int mclk;
	unsigned int fs;
	unsigned int clk_src_sel;
	unsigned int dmic_clk_threshold;
};

/* System Clock Source Select */
enum {
	INTERNAL_BUF_MCLK,
	EXTERNAL_MCLK,
};

struct nau8811_src_attr {
	int param;
	unsigned int val;
};

enum {
	NAU8811_MCLK_FS_RATIO_256,
	NAU8811_MCLK_FS_RATIO_400,
	NAU8811_MCLK_FS_RATIO_500,
	NAU8811_MCLK_FS_RATIO_NUM,
};

struct nau8811_srate_attr {
	unsigned int fs;
	unsigned int mclk_src[NAU8811_MCLK_FS_RATIO_NUM];
};

struct nau8811_osr_attr {
	unsigned int osr;
	unsigned int clk_src;
};

struct nau8811_dmic_speed {
	unsigned int param;
	unsigned int val;
};


#endif  /* __NAU8811_H__ */
